Designs of integrated circuit semiconductor devices have developed rapidly, particularly with increased use of information processing technologies. To meet various demands when using these information processing technologies, semiconductor devices may need to provide high response speeds and/or large storage capacities. Hence, semiconductor manufacturing technologies have been developed to provide semiconductor devices having high integration densities, improved reliability, rapid response speeds, etc.
As semiconductor devices become more highly integrated, a cell of a semiconductor device (such as a memory device) may be significantly reduced in size, resulting in reduction of processing margins and/or dimensions of patterns and/or wirings. Moreover, the patterns and/or wirings may have increased aspect ratios.
In a highly integrated semiconductor device, numerous patterns and/or wirings may be formed on a semiconductor substrate. Some patterns and/or wirings are insulated from one another while other patterns and/or wirings are electrically connected. For example, a very large scaled integrated (VLSI) circuit generally may have a multi-layered structure in which patterns and/or wirings are electrically connected.
As semiconductor devices have been manufactured with design rules of below about 0.1 μm, contact holes for connecting one pattern and/or wiring to another pattern and/or wiring may have minute sizes, and intervals between the patterns and/or wirings may be greatly reduced while aspect ratios may be increased. To provide processing margins when forming contact holes, self-aligned contact formation processes have been developed. In particular, spacers may be formed on sidewalls of the patterns and/or the wirings in a self-aligned contact formation process so that intervals between the patterns and/or the wirings may be reduced. When an insulation layer is formed to cover narrowly disposed patterns and/or the wirings, voids may be generated in the insulation layer because the intervals between the patterns and/or the wirings are too narrow and the design rule of the semiconductor device may be reduced. Bridges may thus be generated in the voids between the patterns and/or the wirings and may cause a failure of the semiconductor device as well as reduce throughput of a semiconductor manufacturing process.
U.S. Pat. No. 6,423,630 discusses forming an interlayer insulation layer on a semiconductor substrate where metal patterns having high aspect ratios are formed.
FIGS. 1A to 1C are cross sectional views illustrating a conventional method of forming an interlayer insulation layer on a substrate having metal patterns of high aspect ratios as disclosed in U.S. Pat. No. 6,423,630. The disclosure of U.S. Pat. No. 6,423,630 is incorporated herein by reference in its entirety.
Referring to FIG. 1A, metal patterns 12 are provided on a substrate 10. A first insulation material 16 is formed via a chemical vapor deposition (CVD) process on the substrate 10 and metal patterns 12. Because the first insulation layer 16 may not completely fill gaps between the metal patterns 12, voids 14 having long elliptical shapes may be formed in the first insulation layer 16.
As shown in FIG. 1B, the first insulation layer 16 may be partially removed by a chemical mechanical polishing (CMP) process, thereby forming first insulation layer patterns 16a that open the voids in the first insulation layer 16 and that expose upper faces of the metal patterns 12. Here, the voids 14 may be relatively narrow at their openings after the CMP process because wider portions of the voids may be more closely adjacent to the substrate 10.
Referring to FIG. 1C, a second insulation material may be formed on the first insulation layer patterns 16a by a CVD process to cover the narrowly opened voids. Thus, a second insulation layer 18 may be formed on the first insulation layer patterns 16a to thereby form a combined interlayer insulation layer on the substrate.
When the second insulation layer 18 is formed on the first insulation layer pattern 16a including the narrowly opened voids, however, the voids may not be completely filled with the second insulation layer 18. Bridges may thus be generated between the metal patterns 12 in a successive process. In addition, because the first insulation layer pattern 16a is formed using the CMP process, the metal patterns 12 may be damaged during the CMP process and the throughput of a semiconductor manufacturing process may be reduced.